Board edge clearance violation

Diagnostic signature

Board edge clearance violation

A KiCad DRC error indicating that a copper object (such as a track, pad, via, or copper zone) is placed closer to the board outline or a routed slot than the configured minimum copper-to-edge clearance.

What it means

The Design Rules Checker (DRC) has detected a copper feature that violates the allowed minimum distance to the physical edge of the printed circuit board. In KiCad, board edges are defined by graphical shapes (such as lines and arcs) drawn on the `Edge.Cuts` layer. Additionally, the DRC treats non-plated through hole (NPTH) oval slots—which are typically routed by the manufacturer rather than drilled—as board edges. If any copper object, such as a routing track, component pad, via, or copper pour (zone), is located within this restricted margin, a violation is raised. Enforcing a pull-back distance between copper and the board outline prevents physical damage to the traces during the final board routing or V-scoring processes, avoids leaving exposed copper that could short to a metal enclosure, and reduces the risk of copper delamination during depanelization.

Why it happens

The absolute physical distance between the geometry of a copper object and the nearest board outline segment (on `Edge.Cuts`) or routed NPTH oval hole is smaller than the active constraint limit. The limit enforcing this is either the global "Copper to edge clearance" defined in the board's constraints setup (File -> Board Setup -> Design Rules -> Constraints), or a targeted clearance rule defined by a custom DRC rule expression. Common triggers include placing surface mount or through-hole components too close to the board perimeter, editing the board outline so that it cuts into existing routing, failing to define an adequate edge setback for a filled copper zone, or placing a routed mounting slot immediately adjacent to copper traces.

Minimal reproduction

(kicad_pcb (version 20240108) (generator "pcbnew")
  (setup
    (board_design_settings
      (copper_edge_clearance 0.5)
    )
  )
  (segment (start 10 10) (end 20 10) (width 0.2) (layer "F.Cu") (net 0))
  (gr_line (start 10 10.2) (end 20 10.2) (layer "Edge.Cuts") (stroke (width 0.1) (type solid)))
)

How to fix it

Increase the physical distance between the copper feature and the board edge, or adjust the clearance constraints if the manufacturing capabilities safely permit a tighter tolerance.

```KiCad PCB S-Expression
(kicad_pcb (version 20240108) (generator "pcbnew")
  (setup
    (board_design_settings
      (copper_edge_clearance 0.5)
    )
  )
  (segment (start 10 10) (end 20 10) (width 0.2) (layer "F.Cu") (net 0))
  (gr_line (start 10 11.0) (end 20 11.0) (layer "Edge.Cuts") (stroke (width 0.1) (type solid)))
)
```

Step 1

• 1. Open the DRC report to identify the exact copper object (track, pad, via, or zone) and the corresponding Edge.Cuts graphic triggering the violation.

Step 2

• 2. If the board outline is correct, select the offending copper object and move it further inward from the board edge so the gap satisfies the minimum clearance.

Step 3

• 3. If the copper object's placement is deliberate and correct, adjust the board outline on the Edge.Cuts layer to provide more room around the copper.

Step 4

• 4. If the global clearance constraint is overly conservative for your specific board manufacturer, navigate to 'File -> Board Setup -> Design Rules -> Constraints' and reduce the 'Copper to edge clearance' value to match your fabrication house's capabilities.

Step 5

• 5. If the pad is an intended edge connector (like a gold finger), ensure its pad type is specifically set to 'Edge Connector' in its properties, which automatically permits it to overlap the board edge.

Step 6

• 6. Re-run the DRC to verify the violation is resolved.

Upstream references

PCB Editor | 9.0 | English | Documentation - KiCad Docs

Issue #14199: Edge connector pads throw a board edge violation in DRC