Bus Entry needed (KiCad ERC)

Diagnostic signature

Bus Entry needed

Explains the KiCad ERC violation triggered when the automated EAGLE importer fails to generate a graphical bus entry for a wire connecting to a bus.

What it means

In the KiCad schematic editor, wires that conceptually join buses must connect via a specific graphical 'bus entry' segment (a short, 45-degree angled line) or rely entirely on correctly matching net labels [1]. When a user imports a legacy schematic from Autodesk EAGLE into KiCad, the KiCad importer runs heuristics to automatically place these graphical bus entries, maintaining the visual topology of the original design. If the importer cannot confidently resolve the intersection between a wire and a bus, it leaves the connection graphically incomplete. Rather than silently failing or making incorrect electrical assumptions, the Electrical Rules Checker (ERC) emits a specific marker to alert the designer that manual intervention is necessary. This diagnostic is exclusively relevant to imported EAGLE projects.

Why it happens

The upstream KiCad EAGLE import engine triggers this ERC violation when it parses a wire-to-bus junction in an EAGLE XML file but cannot automatically determine the proper orientation, length, or insertion point for a valid KiCad `bus_entry` object [1]. This commonly occurs with dense, overlapping, vaguely aligned, or non-orthogonally routed nets in the legacy schematic. When the importer's heuristics give up, it forces the ERC to flag the ambiguous junction so a human operator can manually verify and draw the correct bus entry [1].

Minimal reproduction

<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="9.6.2">
<drawing>
<schematic>
<libraries/>
<parts/>
<sheets>
<sheet>
<nets>
<bus name="A[0..3]">
<segment>
<wire x1="0" y1="0" x2="0" y2="50" width="0.762" layer="92"/>
</segment>
</bus>
<net name="A0" class="0">
<segment>
<wire x1="-20" y1="20" x2="0" y2="20" width="0.1524" layer="91"/>
</segment>
</net>
</nets>
</sheet>
</sheets>
</schematic>
</drawing>
</eagle>

How to fix it

Manually insert a graphical Bus Entry where the wire meets the bus to resolve the EAGLE import failure.

```xml
(kicad_sch (version 20231120) (generator "eeschema")
  (paper "A4")
  (wire (pts (xy 90 100) (xy 107.46 100)) (stroke (width 0) (type default)))
  (bus (pts (xy 110 90) (xy 110 110)) (stroke (width 0) (type default)))
  (bus_entry (at 107.46 100) (size 2.54 2.54) (stroke (width 0) (type default)))
)
```

Step 1

• Locate the 'Bus Entry needed' ERC violation marker in the KiCad schematic editor.

Step 2

• Delete any overlapping or excessive straight wire segments that were improperly imported directly onto the bus line.

Step 3

• Select the 'Add a wire to bus entry' tool from the right toolbar (default shortcut: 'Z').

Step 4

• Click to place the 45-degree bus entry segment, bridging the gap between the bus line and the wire end.

Step 5

• Ensure the attached wire has a local net label that matches a valid member of the bus (e.g., 'A0' for bus 'A[0..3]').

Step 6

• Rerun the Electrical Rules Checker (ERC) to confirm the violation is resolved.

Upstream references

KiCad 8.0 Schematic Editor Documentation: List of ERC checks

KiCad Source Code: eeschema/erc_item.cpp