KiCad DRC: Clearance violation

Diagnostic signature

Clearance violation

Design Rule Check (DRC) error emitted when two copper objects belonging to different electrical nets are placed closer together than the minimum clearance distance configured in board constraints, netclasses, footprint/pad overrides, or custom DRC rules.

What it means

KiCad's PCB Editor Design Rules Checker (DRC) evaluates the geometric distance between all distinct copper entities on the same conductive layer (including track segments, arcs, vias, pads, filled zones, and graphical copper shapes). A 'Clearance violation' (internal diagnostic code DRCE_CLEARANCE) indicates that the calculated shortest physical distance between two copper objects belonging to different electrical nets is strictly less than the required clearance threshold. The applicable threshold is resolved dynamically by taking the largest constraint among the board-level minimum copper clearance, the netclass clearances of both participating nets, footprint or pad clearance overrides, and any matching user-defined custom DRC rules. The diagnostic report includes the controlling rule name or netclass, the required clearance value, and the measured actual distance.

Why it happens

KiCad triggers a Clearance violation during DRC execution or interactive router verification in the following scenarios: - Interactive routing or manual trace manipulation: A track or via was routed or dragged too close to an adjacent trace, via, or pad of a different net, violating the netclass spacing or board constraint. - Unfilled or stale copper zones: Footprints, pads, or traces were added or moved inside an existing filled zone without running a zone refill (hotkey 'B'), causing the stale zone polygon fill to overlap or sit too close to unassociated copper features. - Pad or footprint property overrides: A pad or footprint has an explicit local clearance override set in its properties dialog that exceeds the space available between adjacent component pads or routing corridors. - Strict Netclass assignments: A net assigned to a class with larger spacing requirements (such as a high-voltage, high-current, or differential pair class) is routed through areas designed only for standard default clearances. - Custom DRC rules: A custom rule (for example, (constraint clearance (min ...))) matched one or both objects and mandated a larger clearance than standard netclass settings.

Minimal reproduction

(kicad_pcb
  (version 20240108)
  (generator "kicad-cli")
  (general
    (thickness 1.6)
    (legacy_teardrops no)
  )
  (paper "A4")
  (layers
    (0 "F.Cu" signal)
    (31 "B.Cu" signal)
    (44 "Edge.Cuts" user)
  )
  (setup
    (pad_to_mask_clearance 0)
  )
  (net 0 "")
  (net 1 "NetA")
  (net 2 "NetB")
  (net_class "Default" "Default net class"
    (clearance 0.25)
    (trace_width 0.25)
    (via_dia 0.6)
    (via_drill 0.3)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net "NetA")
    (add_net "NetB")
  )
  (segment (start 100 100) (end 110 100) (width 0.25) (layer "F.Cu") (net 1))
  (segment (start 100 100.35) (end 110 100.35) (width 0.25) (layer "F.Cu") (net 2))
)

How to fix it

Resolve the clearance violation by increasing the physical separation between the offending copper elements, refilling modified copper zones, or modifying the controlling clearance constraints in Board Setup if the tighter spacing complies with the manufacturing process.

```kicad_pcb
(kicad_pcb
  (version 20240108)
  (generator "kicad-cli")
  (general
    (thickness 1.6)
    (legacy_teardrops no)
  )
  (paper "A4")
  (layers
    (0 "F.Cu" signal)
    (31 "B.Cu" signal)
    (44 "Edge.Cuts" user)
  )
  (setup
    (pad_to_mask_clearance 0)
  )
  (net 0 "")
  (net 1 "NetA")
  (net 2 "NetB")
  (net_class "Default" "Default net class"
    (clearance 0.25)
    (trace_width 0.25)
    (via_dia 0.6)
    (via_drill 0.3)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net "NetA")
    (add_net "NetB")
  )
  (segment (start 100 100) (end 110 100) (width 0.25) (layer "F.Cu") (net 1))
  (segment (start 100 100.60) (end 110 100.60) (width 0.25) (layer "F.Cu") (net 2))
)
```

Step 1

• Inspect the governing rule: Select both colliding objects in the PCB Editor canvas and click 'Inspect' -> 'Clearance Resolution' (or right-click the error in the DRC panel and select 'Clearance Resolution...') to identify the controlling rule, netclass, or constraint.

Step 2

• Reposition or reroute copper: Select the offending track, via, or footprint and move it using 'Drag' ('D') or 'Move' ('M') to create sufficient spacing. When using the interactive router, ensure 'Walk Around' or 'Push and Shove' mode is active to automatically maintain netclass clearances.

Step 3

• Refill copper zones: If a copper zone is involved in the clearance violation, press 'B' on the canvas (or select 'Edit' -> 'Fill All Zones') to recalculate zone clearance boundaries around new or moved board items.

Step 4

• Check pad/footprint overrides: If a footprint pad is causing the violation, open Pad Properties ('E') and ensure the 'Clearance Overrides' -> 'Net fee / Pad clearance' field is set to empty (inherited) or appropriately dimensioned rather than an excessively large custom value.

Step 5

• Adjust constraints if intentional: If tighter spacing is required and supported by your PCB manufacturer capabilities, update the netclass clearance in 'File' -> 'Board Setup...' -> 'Net Classes', the global minimum in 'Constraints', or the corresponding expression in 'Custom Rules'.

Step 6

• Re-run DRC: Open 'Inspect' -> 'Design Rules Checker' and click 'Run DRC' to verify the violation is resolved.

Upstream references

KiCad KiCad 9.0.9, documentation revision 152cd19e — Electrical DRC checks — retrieved 2026-08-11

KiCad Source Code – Copper Clearance DRC Test Provider (drc_test_provider_copper_clearance.cpp)