Creepage Violation

Diagnostic signature

Creepage violation

A 'Creepage violation' DRC error in KiCad indicates that the shortest surface distance between two conductive items is less than the required minimum defined in the board's custom rules.

What it means

In KiCad, a 'Creepage violation' is a Design Rule Check (DRC) error that occurs when the creepage distance—defined as the shortest path along the surface of the PCB's insulating material between two conductive items on different nets—falls below the minimum threshold required by the board's custom rules. Unlike standard clearance, which measures the shortest distance through the air (line-of-sight), creepage calculations account for the PCB surface topology, including paths that wrap around board edges or unplated milled slots on the Edge.Cuts layer. When the DRC engine determines that a surface path connecting two distinct nets violates the user-specified `creepage` constraint, it emits this violation and highlights the offending path in the editing canvas.

Why it happens

The DRC engine emits this diagnostic because two distinct conductive objects (such as pads, vias, traces, or copper zones) are physically placed too close to each other along the continuous surface of the board, violating a custom rule that mandates a larger spacing. This typically occurs in high-voltage designs when components are packed tightly or when the layout designer fails to add an isolation slot to artificially lengthen the surface path between nets. The error can also be triggered if a custom design rule (`kicad_dru`) unintentionally targets low-voltage nets with a high-voltage creepage requirement due to missing or overly broad `condition` statements.

Minimal reproduction

(version 1)
(rule "High Voltage Creepage"
  (constraint creepage (min 5mm))
)

How to fix it

To fix a creepage violation, increase the physical surface distance between the affected conductive items, insert an isolation slot in the Edge.Cuts layer to extend the surface path length, or properly scope the constraint in the custom rules.

```KiCad Custom Rules
(version 1)
(rule "High Voltage Creepage"
  (condition "A.NetClass == 'HV' && B.NetClass == 'HV'")
  (constraint creepage (min 5mm))
)
```

Step 1

• Open the Design Rules Checker (DRC) window and select the reported 'Creepage violation'. KiCad will highlight the calculated minimum creepage path in the PCB Editor canvas.

Step 2

• Check if the rule is correctly applied. If the violation occurs on low-voltage nets, navigate to 'File' > 'Board Setup' > 'Custom Rules' and tighten the `condition` logic so the `creepage` constraint only applies to high-voltage netclasses.

Step 3

• If the rule correctly targets the nets, increase the physical surface distance between them by moving the affected components, footprints, or copper traces further apart.

Step 4

• Alternatively, if components cannot be moved, draw an unplated isolation slot (cutout) on the `Edge.Cuts` layer between the two conductive items. The DRC engine routes the creepage path around the slot, artificially increasing the total surface distance.

Upstream references

PCB Editor | 9.0 | English | Documentation

drc_item.cpp Source File