Items shorting two nets
A Design Rule Check (DRC) error in the KiCad PCB Editor indicating that conductive features assigned to different electrical nets physically intersect or collide.
The PCB layout contains a continuous path of conductive material—such as a track, via, pad, or copper zone—that bridges at least two distinct logical nets defined by the schematic. The DRC engine flags this because a physical connection between differing net identifiers typically implies an unintentional short circuit that will cause electrical failure if manufactured.
This diagnostic is typically raised when routing a trace directly between pads of conflicting nets, when placing vias that intersect an unrelated trace, or when copper zones assigned to different nets overlap without sufficient clearance. It also frequently occurs when a designer intentionally attempts to bridge two nets (for instance, an analog ground and a digital ground) using standard copper tracks instead of deploying a properly configured "Net Tie" footprint, which explicitly instructs the DRC engine to permit the localized bridge.
(kicad_pcb (version 20221018) (generator pcbnew)
(general)
(paper "A4")
(layers
(0 "F.Cu" signal)
)
(setup)
(net 0 "")
(net 1 "Net_A")
(net 2 "Net_B")
(segment (start 0 0) (end 10 0) (width 0.2) (layer "F.Cu") (net 1))
(segment (start 0 0) (end 10 0) (width 0.2) (layer "F.Cu") (net 2))
)
Remove the offending copper bridging the nets, maintain required clearances, or use a dedicated Net Tie footprint if the electrical bridge is intentional.
```KiCad PCB (S-Expression)
(kicad_pcb (version 20221018) (generator pcbnew)
(general)
(paper "A4")
(layers
(0 "F.Cu" signal)
)
(setup)
(net 0 "")
(net 1 "Net_A")
(net 2 "Net_B")
(segment (start 0 0) (end 10 0) (width 0.2) (layer "F.Cu") (net 1))
(segment (start 15 0) (end 25 0) (width 0.2) (layer "F.Cu") (net 2))
)
```