Canonical explanations and fixes for kicad toolchain error signatures.
KiCad's Schematic Editor emits the [pin_not_connected] ERC diagnostic when a symbol pin is left floating without an explicit wire, label, or 'No Connect' flag.
The KiCad Electrical Rules Checker (ERC) reports [pin_not_driven] when an Input or Power Input pin is not connected to a corresponding Output or Power Output pin. This commonly occurs when power is supplied via a passive component, such as a connector or switch, without an explicit power source defined on the net.
The KiCad Schematic Editor's Electrical Rules Checker (ERC) emits a `[pin_to_pin]` diagnostic when two or more connected pins have electrical types that clash according to the project's Pin Conflicts Map, such as connecting two 'Output' pins together.
KiCad's Electrical Rules Check (ERC) emits this diagnostic when a schematic pin is marked with an explicit "No Connection" (NC) flag but is concurrently connected to a wire, bus, label, or component.
The KiCad DRC engine has detected a copper area that necks down to a width smaller than the configured minimum connection width constraint. This commonly occurs at thermal relief spokes, zone fill bottlenecks, or track-to-pad intersections.
The Copper sliver DRC violation in KiCad detects extremely narrow, wedge-shaped protrusions of copper. These tiny slivers pose a hazard during PCB manufacturing because they can detach and cause electrical shorts.
A 'Creepage violation' DRC error in KiCad indicates that the shortest surface distance between two conductive items is less than the required minimum defined in the board's custom rules.
The KiCad Design Rule Checker detected multiple footprints on the PCB sharing the exact same reference designator, causing ambiguity in schematic parity.
The KiCad PCB Editor (pcbnew) DRC engine triggers an "Extra footprint" violation when a footprint exists on the board but lacks a matching symbol in the schematic and is not explicitly marked as a board-only item.
KiCad's Electrical Rules Checker (ERC) reports this warning when a global label appears only once in the entire schematic hierarchy, indicating it fails to form an inter-sheet connection.
An Electrical Rules Check (ERC) diagnostic in KiCad that warns when a global label is placed only once across the entire schematic, indicating that it does not form any global connections.
The KiCad Electrical Rules Checker (ERC) detected a symbol pin defined as an Input connected to a net that lacks a valid driving source.
An Electrical Rules Check (ERC) diagnostic emitted when a component's power input pin connects to a net without an active power output source. This frequently occurs when power routes through passive components or generic connectors.
A Design Rule Check (DRC) error in the KiCad PCB Editor indicating that conductive features assigned to different electrical nets physically intersect or collide.
This KiCad Electrical Rules Checker (ERC) violation occurs when a net label is placed precisely at the intersection of two crossing, unconnected wires, making it ambiguous which net the label should name.
During an Electrical Rules Check (ERC) in the Schematic Editor, KiCad emits this diagnostic when a local, global, or hierarchical label is placed on the schematic but its attachment point is not electrically connected to any wire, pin, or bus.
KiCad's Electrical Rules Checker (ERC) warns when a local label and a global label share the exact same text identifier, preventing ambiguous connectivity and unlinked nets across hierarchical schematic sheets.
The KiCad PCB Editor Design Rule Checker (DRC) flags a 'Missing footprint' violation when a schematic symbol has no corresponding physical footprint placed on the board layout. This usually happens if the board has not been updated from the schematic, or if the assigned footprint is invalid.
The KiCad Electrical Rules Checker (ERC) reports a "Pin not connected" violation when a schematic symbol pin is left floating without an explicit no-connect flag.
KiCad emits this DRC warning when a silkscreen object intersects with a solder mask opening for a pad or via, which can lead to illegible markings or defective solder joints during manufacturing.
A DRC violation in KiCad indicating that a single continuous solder mask opening exposes multiple copper items belonging to different nets. This lack of a solder mask dam between the items increases the risk of solder bridging and short circuits during assembly.
An ERC violation indicating that a symbol pin or wire endpoint does not align with the standard 50-mil schematic connection grid, which can prevent correct electrical connectivity.
KiCad PCB Editor's Design Rule Check (DRC) triggers this violation when a pad cannot connect to a surrounding solid copper zone with the required minimum number of thermal relief spokes.
A Design Rule Check (DRC) warning indicating that a routed copper track segment does not terminate at a valid electrical node, such as a pad, via, or another contiguous track.
The KiCad Design Rule Checker (DRC) emits the `length_out_of_range` violation when a routed track or differential pair falls outside the minimum and maximum length bounds specified by custom constraints. This diagnostic ensures signal integrity by strictly enforcing propagation delays and physical trace lengths.
A "no connection" flag is present on the schematic canvas but is not attached to any component pin or label, triggering an Electrical Rules Check (ERC) warning.
KiCad's Schematic Editor (eeschema) Electrical Rules Checker triggers this warning when a wire segment fails to terminate at a valid electrical node, leaving it floating in the schematic.
A Design Rule Check (DRC) violation indicating a via fails to connect copper on multiple layers, rendering its through-hole functionality useless.
A KiCad Electrical Rules Check (ERC) diagnostic indicating that a schematic wire segment has an open end that does not terminate at a valid connection point, such as a component pin, label, power port, or another wire.
Explains the KiCad ERC violation triggered when the automated EAGLE importer fails to generate a graphical bus entry for a wire connecting to a bus.